//////////////////////////////////////////////////////////////////////////////////
// INSTITUTION:    Xidian University
// DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
// 
// Create Date:    16:53:58 02/14/2016 
// Design Name:    FREQUENCY_DIVIDER 
// Module Name:    FREQUENCY_DIVIDER 
// Project Name:   PWM
// Target Devices: EP3C16F484C6
// Tool versions:  Quartus II 13.1
// Design Lauguage:Verilog-HDL
// Dependencies:   -
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: DE0 Board Input Freguency = 50 MHz
//                      Destiny Output  Freguency =  1 Hz
//
//////////////////////////////////////////////////////////////////////////////////
module FREQUENCY_DIVIDER (
									input 		i_sys_clk,
									input			i_sys_rst,
									output reg	o_div_clk
								);
								
parameter  sys_clk_fre_value = 32'd50000000;
parameter  div_clk_fre_value = 100000;
parameter  div_count_value = sys_clk_fre_value/div_clk_fre_value/2-32'd1;

reg [31:0] r_div_count;								

always @ (posedge i_sys_rst or posedge i_sys_clk)
begin
	if( i_sys_rst )begin
		r_div_count <= 32'd0;
		o_div_clk <= 1'b0;
	end else begin
		if( r_div_count == div_count_value )begin
			r_div_count <= 32'd0;
			o_div_clk <= ~o_div_clk;
		end else begin
			r_div_count <= r_div_count + 32'd1;
		end			
	end
end

endmodule
